Analog VLSI Neural Networks: A Special Issue of Analog by Yoshiyasu Takefuji (auth.), Yoshiyasu Takefuji (eds.) PDF

By Yoshiyasu Takefuji (auth.), Yoshiyasu Takefuji (eds.)

ISBN-10: 1461365929

ISBN-13: 9781461365921

ISBN-10: 1461535824

ISBN-13: 9781461535829

This ebook brings jointly in a single position very important contributions and cutting-edge study within the speedily advancing sector of analog VLSI neural networks.
The publication serves as an exceptional reference, supplying insights into probably the most very important concerns in analog VLSI neural networks learn efforts.

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Extra resources for Analog VLSI Neural Networks: A Special Issue of Analog Integrated Circuits and Signal Processing

Example text

During normal operation, these bias lines are all set at a common bias voltage used to establish the naive weight value. When the weights are to be updated, the bias lines corresponding to active mitral cells are switched to a high-voltage programming line via high-voltage switches, while on the piriform side, the reference inputs of current conveyors for winning piriform cells are strobed to the negative rail, pulling the drains of the weighting transistors for those cells to nearly the same potential.

Circuit Designs Many of the functions which are required to implement the model as described above may be achieved with well-known analog building blocks. In designing our circuitry, a current-mode approach was adopted for reasons of improved bandwidth and noise immunity. ) A settling time on the order of several hundred nanoseconds was targeted for feedforward excitatory or feedback inhibitory phases of network operation. Current-mode circuits in addition permit a simple solution to the proposed bidirectional, time-multiplexed use of the weight matrix.

Will increase both capacitance at the feedback node and the bypass current which discharges capacitance at the input node via M 1 and M2. A) at the initial cycle in dc tests. Simulations indicate the circuit to be operable at a clocking speed of 10 MHz. 2. 5 V total amplitude (control gate to drain) were used, applied in pulses of several durations and rise times. Positive-going control gate pulses overlapped negative-going drain pulses to prevent channel current flow. Figure 10 depicts shift in transistor threshold voltage (relative to the control gate) observed in one of these tests.

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Analog VLSI Neural Networks: A Special Issue of Analog Integrated Circuits and Signal Processing by Yoshiyasu Takefuji (auth.), Yoshiyasu Takefuji (eds.)

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